Job Description
Join Trust Recruit as a Digital IC Design Engineer and drive front end RTL design and DFT ready ASIC development in the East Region. You will work with RTL Verilog and SystemVerilog, optimize logic synthesis, and deliver silicon-ready digital blocks for high performance applications. This role blends hands-on engineering with rigorous verification, design-for-test (DFT) implementation, and close collaboration across multi disciplinary teams to ensure robust, manufacturable designs.
As part of the team, you will engage in the full design flow from architectural exploration to implementation, verification, and sign-off. You will leverage cutting edge EDA tools, apply best practices in coding standards, and contribute to power, performance, and area optimization. The environment rewards initiative, cross functional communication, and a focus on delivering high quality silicon while maintaining project timelines.
The ideal candidate thrives in a fast paced, collaborative setting and brings a strong foundation in RTL design, logic synthesis, and DFT techniques. If you are passionate about innovation in digital design and eager to grow within a supportive, results-driven organization, this opportunity is for you.
Responsibilities
- Design and optimize RTL blocks using Verilog and SystemVerilog for complex digital architectures.
- Lead logic synthesis efforts to meet timing, area, and power targets across multiple projects.
- Implement and validate DFT structures such as scan chains and BIST, and drive DFT sign-off.
- Develop and maintain comprehensive test benches and verification plans; collaborate with V&V teams.
- Coordinate with back end and physical design teams to ensure robust timing closure and linting adherence.
- Review designs with peers, write technical documentation, and participate in design reviews.
- Mentor junior engineers and contribute to process improvements and EDA tool optimization.
Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 4+ years of hands-on digital IC design experience, with ASIC/SoC exposure preferred.
- Strong proficiency in Verilog and SystemVerilog; knowledge of VHDL is a plus.
- Deep understanding of logic synthesis, timing, power, and DFT techniques (scan, BIST).
- Experience with EDA tool suites (Synopsys: Design Compiler, PrimeTime; Cadence: Genus, Innovus, Xcelium; Mentor tools).
- Scripting ability in Python and TCL; comfortable in Unix/Linux environments.
- Excellent problem-solving, communication, and collaborative skills for cross-functional work.