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Physical Design Engineer

ByteDance
Singapore
Estimated Salary
SGD 100.000 – SGD 150.000
Posted Date
2 Mei 2026
Application Deadline
2 Mei 2027

Job Description

Join ByteDance's Silicon Platform Team, the heart of our chip development R&D. We're seeking a visionary Physical Design Engineer to drive the full lifecycle of semiconductor innovation. As a key architect of next-generation chips, you'll transform complex digital designs into high-performance silicon solutions while optimizing power, area, and timing. Collaborate with cross-functional teams to push the boundaries of semiconductor technology and deliver cutting-edge products that impact millions of users globally.

This role offers unparalleled exposure to advanced process nodes and state-of-the-art EDA tools. You'll own physical implementation from floorplanning to final tapeout, ensuring manufacturability and performance excellence. ByteDance provides a dynamic environment where your expertise will directly influence the future of computing technology.

Responsibilities

  • Lead end-to-end physical design implementation for complex ASICs/SoCs including floorplanning, placement, CTS, routing, and timing closure
  • Perform comprehensive static timing analysis (STA), power analysis, and physical verification (DRC/LVS/ERC)
  • Optimize designs for power-performance-area (PPA) targets across advanced process nodes
  • Develop and implement robust physical design methodologies and automation flows
  • Collaborate with architecture and verification teams to ensure design closure
  • Interface with foundries to resolve process-specific design challenges
  • Drive continuous improvement of physical design best practices and tool flows

Qualifications

  • Bachelor's or Master's degree in Electrical/Computer Engineering or related field
  • 5+ years of hands-on physical design experience with digital ASICs/SoCs
  • Expertise in Cadence Innovus/Synopsys IC Compiler and EDA tools
  • Strong understanding of semiconductor design flows and timing closure methodologies
  • Experience with advanced process nodes (7nm, 5nm, 3nm) and foundry PDKs
  • Proven track record in resolving complex physical design issues
  • Excellent problem-solving skills and ability to work in fast-paced environments

Required Skills

Physical Design ASIC SoC Timing Closure STA Power Analysis DRC LVS Cadence Synopsys PPA CTS Floorplanning Place & Route Semiconductor

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