Job Description
Are you a seasoned hardware engineering professional with a passion for hardware-assisted verification? UST Global is seeking a Senior Emulation Engineer to join our elite team in Kulim, Kedah. In this pivotal role, you will be at the forefront of silicon development, bridging the gap between RTL and high-performance emulation platforms.
You will be responsible for architecting and managing complex RTL-to-model build flows, ensuring seamless integration for large-scale SoC designs. Your work will directly accelerate the debug cycles and performance verification of next-generation hardware. If you thrive in high-stakes environments and possess deep expertise in emulation technologies, we invite you to help us push the boundaries of semiconductor innovation.
Responsibilities
- Architect and maintain complex RTL-to-model build flows to support hardware development.
- Deploy and optimize emulation platforms (e.g., Palladium, ZeBu, or Veloce) for SoC design verification.
- Collaborate with cross-functional teams to resolve complex hardware/software debug challenges.
- Develop and implement automation scripts using Python, Perl, or Tcl to enhance build throughput.
- Manage capacity planning and regression testing environments to ensure high availability for global design teams.
- Conduct performance analysis to identify bottlenecks in the emulation build process.
- Provide technical mentorship to junior engineers regarding simulation and emulation best practices.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of experience in hardware emulation, simulation, or FPGA-based prototyping.
- Strong proficiency in Verilog, SystemVerilog, and RTL design principles.
- Solid understanding of EDA tool flows and hardware emulation methodology.
- Proven expertise in scripting languages (Python, Shell, Tcl) for flow automation.
- Excellent analytical skills with a focus on deep-dive technical debugging.
- Experience working in an Agile/DevOps-oriented hardware development lifecycle is a plus.